Adders are generally of five types:

1.Ripple Carry Adder:

The Ripple carry adder(RCA) consists of a building block named Half Adder(HA) which is cascaded to form a Full Adder(FA). These buildingblocks HAs and FAs are also the building blocks of all types of adders.The n full adders are cascaded to form n bit RCA.

The full adder has three input pins(input Ai,input Bi,carryin Ci) and two output pins(Sum and Ci+1).Its equations are:

Sum=Ai^Bi^Ci

Ci+1=Ai.Bi+Bi.Ci+Ai.Ci

2. Carry Lookahead Adder:

The Carry Lookahead Adder(CLA) reduces the delay as that in RCA. Let Gi=Ai.Bi, and Pi=Ai^Bi, then Ci+1=Gi+Pi.Ci.

The expressions for Sum and Ci+1 is then defined completely in terms of input pins rather wait for input carry to appear.

3. Carry Select Adder:

The carry select adder uses duplicate modules for each combination of input carry(i.e. 1 and 0).The multiplexers then select the appropriate sum and carry output according to the carry output of the preceding stages.

4. Carry Skip Adder:

The carry skip adder are as fast as carry lookahead adders which are the fastest adders but its spped decreases to about 20-30% if input operands are 64-bit or more. In these adders we divide the input bit stream into various blocks and make use of two observations:

-if each element of the two bit streams are unequal,i.e. Ai!=Bi than the carry input of the block is equal to the carry input.

-if each element of the two bit streams are equal,i.e. Ai=Bi than the carry input of the block is opposite of the carry input.

5. Carry Save Adder:

The carry save adder reduces the addition of three elements into addition of two elements,i.e. if you want sum of nine numbers it reduces it into sum of six numbers. In first step the sum of three numbers is calculated without bothering for the carry.During the second step only carry is calculated which is then added to the generated sum to give the required sum. 

Suppose your flip-flop is positive edgetriggered. time for which data should be stable prior to positive edge clock is called setup is called setup time constraint.

Time for which data should be stable after the positive edge of clock is called as hold time constraint.

If any of these constraints are violate d then flip-flop will enter in meta stable state, in which we cannot determine the output of flip-flop.

there are two equation:

1. Tcq + Tcomb > Tskew + Thold

2. Tcq + Tcomb > Tskew + T - Tsetup

Tcq is time delay when data enters the flip flop and data comes at output of flip flop.

Tcomb is the logic delay between two flip flop.

Tskew is the delay of clock to flip flop: suppose there are two flip flop, if clock reaches first to source flip flop and then after some delay to destination flip flop, it is positive skew and if vice versa then negative  skew. 

so if you take 2 eq you will see that setup time is the determining factor of clock's time period.

Pass input to XOR and give their outputs to OR gate, if your output is 0 both 8-bit signals are same.

OR

Pass input to XNOR and give their outputs to AND gate, if your output is 1 both 8-bit signals are same. 

Sum of temperatures on 1st, 2nd, 3rd and 4th days = (58 * 4) = 232 degrees ... (1)

Sum of temperatures on 2nd, 3rd, 4th and 5th days - (60 * 4) = 240 degrees  ....(2)

Subtracting (1) From (2), we get :

Temp, on 5th day  - Temp on 1st day  = 8 degrees.

Let the temperatures on 1st and 5th days be 7x and 8x degrees respectively.

Then, 8x - 7x = 8 or x = 8.

Temperature on the 5th day = 8x = 64 degrees.

Middle numbers  =  [(10.5 x 6 + 11.4 x 6) - 10.9 x 11] = (131.4 - 119-9) = 11.5.

Total age of 4 members, 10 years ago = (24 x 4) years = 96 years.

Total age of 4 members now = [96 + (10 x 4)] years = 136 years.

Total age of 6 members now = (24 x 6) years = 144 years.

Sum of the ages of 2 children = (144 - 136) years = 8 years.

Let the age of the younger child be x years.

Then, age of the elder child = (x+2) years.

So, x+(x+2) =8 <=> x=3

Age of younger child  =  3 years.

Use the concept of register-retiming.

divide the totla combinatorial delay in two segments such that individually the delay is less the clock period.

this can be done by inserting a flip-flop in the combinational path.

e.g.,

clock period --- 5 ns

total cominational delay ---- 7

then divide the 7ns path in two path of 4 or 3 (best resutls are obtained if delays are  same for both path i.e 3.5ns) by inserting a flip-flop in between.

Total quantity of petrol consumed in 3 years =(4000/7.50+4000/8+4000/8.50)  liters

                                                         = 4000(2/15+1/8+2/17) liters                                                   

                                                         = 76700/51 liters

Total amount spent = Rs. (3 x 4000) = Rs. 12000.

Average cost = Rs. (12000*51/76700) = Rs. 7.98.