L Search

Q:

A student was asked to find the arithmetic mean of the numbers 3, 11, 7, 9, 15, 13, 8, 19, 17, 21, 14 and x. He found the mean to be 12. What should be the number in place of x ?

A) 6	B) 7
C) 8	D) 9

Answer & Explanation Answer: B) 7

Explanation:

Clearly, we have (3 + 11 + 7 + 9 + 15 + 13 + 8 + 19 + 17 + 21 + 14 + x) / 12 = 12.

or 137 + x = 144 or x = 144 - 137 = 7.

Report Error

View Answer Report Error Discuss

Filed Under: Average

Q:

The average price of 10 books is Rs. 12 while the average price of 8 of these books is Rs. 11.75. Of the remaining two books, if the price of one book is 60% more than the price of the other, what ia the pice of each of these two books ?

A) 16,12	B) 10,16
C) 23,9	D) 8,7

Answer & Explanation Answer: B) 10,16

Explanation:

Total pice of the two books = Rs. [(12 x 10) - (11.75 x 8)]

= Rs. (120 - 94) = Rs. 26.

let the price of one book be Rs. x

Then, the price of other book = Rs. (x + 60% of x) = Rs.(x+(3/5)x) = Rs. (8/5)x

So, x+(8/5)x =26 <=> x =10

The prices of the two books are Rs. 10 and Rs. 16

Report Error

View Answer Report Error Discuss

Filed Under: Average

Q:

The average price of three items of furniture is Rs. 15000. If their prices are in the ratio 3:5:7, the price of the cheapest item is :

A) 6000	B) 7000
C) 8888	D) 9000

Answer & Explanation Answer: D) 9000

Explanation:

Let their prices be 3x, 5x and 7x.

Then, 3x + 5x + 7x = (15000 * 3) or x = 3000.

Cost of cheapest item = 3x = Rs. 9000.

Report Error

View Answer Report Error Discuss

Filed Under: Average

Q:

What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?

Answer

Suppose your flip-flop is positive edgetriggered. time for which data should be stable prior to positive edge clock is called setup is called setup time constraint.

Time for which data should be stable after the positive edge of clock is called as hold time constraint.

If any of these constraints are violate d then flip-flop will enter in meta stable state, in which we cannot determine the output of flip-flop.

there are two equation:

1. Tcq + Tcomb > Tskew + Thold

2. Tcq + Tcomb > Tskew + T - Tsetup

Tcq is time delay when data enters the flip flop and data comes at output of flip flop.

Tcomb is the logic delay between two flip flop.

Tskew is the delay of clock to flip flop: suppose there are two flip flop, if clock reaches first to source flip flop and then after some delay to destination flip flop, it is positive skew and if vice versa then negative skew.

so if you take 2 eq you will see that setup time is the determining factor of clock's time period.

Workspace

Report Error

View answer Workspace Report Error Discuss

Subject: Hardware

Q:

1.Water boils at 100 degree C

2.Water freezes at 0 degree C

Conclusion: At low pressure ,water boils at lower temperature

The conclusion drawn is

A) True	B) false
C) either probably true or probably false	D) Irrelavent

Answer & Explanation Answer: D) Irrelavent

Explanation:

It is irrelavent

Report Error

View Answer Report Error Discuss

Filed Under: Verification of Truth of the statement

Q:

Give a circuit to divide frequency of clock cycle by two?

Answer

You can divide the frequency of a clock by just implementing T Flip flop.

Give clock as clock input and tie the T input to logic 1.

Workspace

Report Error

View answer Workspace Report Error Discuss

Subject: Hardware

Q:

How do you detect if two 8-bit signals are same?

Answer

Pass input to XOR and give their outputs to OR gate, if your output is 0 both 8-bit signals are same.

OR

Pass input to XNOR and give their outputs to AND gate, if your output is 1 both 8-bit signals are same.

Workspace

Report Error

View answer Workspace Report Error Discuss

Subject: Hardware

Q:

1.Oxygen is a gas

2.This cylinder contains gas

Conclusion: This cylinder contains Oxygen

The conclusion drawn is

A) True	B) Probably true
C) False	D) Irrelavent

Searching for "L"

Quick Links