Technical Questions

One way is shorting the two inputs of the NAND gate and passing the input.

truth table:

A B output

1 1 0

0 0 1

The second way is passing the input to only one input (say A) of the NAND gate. Since the other input  (say B is floating, it is always logic one.

Truth table:

A B output

1 1 0 

0 1 1

TRUTH TABLE FOR HALF ADDER

A    B  SUM  CARRY

0    0    0         0

0    1    1         0

1    0    1         0

1    1    0         1

INPLEMENTATION:

For SUM, The two inputs A and B are given to XOR gate.

For Carry, The two inputs A and B are given to AND gate.

A SIPO and AND gate circuit can detect this sequence.The output of SIPO is connected to a four input AND gate ,the third SIPO output should be connected through a NOT gate.When the 1101 sequence is loaded in to the SIPO the AND output goes HIGH otherwise keeps LOW.

Use the concept of register-retiming.

divide the totla combinatorial delay in two segments such that individually the delay is less the clock period.

this can be done by inserting a flip-flop in the combinational path.

e.g.,

clock period --- 5 ns

total cominational delay ---- 7

then divide the 7ns path in two path of 4 or 3 (best resutls are obtained if delays are  same for both path i.e 3.5ns) by inserting a flip-flop in between.

The Transmission-Gate's input is connected to the D_LATCH data input (D), the control input to the Transmission-Gate is connected to the D-Latch enable inputs (EN) and the Transmission-Gate outputs is the D_LATCH output(Q)

SIM is Set Interrupt Mask. Used to mask the hardware interrupts.

RIM is Read Interrupt Mask. Used to check whether the interrupt is Masked or not.

In 8086 Carry flag, Parity flag, Ausiliary caarry flag, Zero flag, Overflow flag, Trace flag, Interrupt flag, Direction flag, and Sign flag.

FIFO (First In First Out) stack is used in 8086. In this type of Stack the First Stored Information is retrieved first.