Questions

Use the concept of register-retiming.

divide the totla combinatorial delay in two segments such that individually the delay is less the clock period.

this can be done by inserting a flip-flop in the combinational path.

e.g.,

clock period --- 5 ns

total cominational delay ---- 7

then divide the 7ns path in two path of 4 or 3 (best resutls are obtained if delays are  same for both path i.e 3.5ns) by inserting a flip-flop in between.

An Egg is more useful when it is broken than it is not.

“Verify Scope is the process of formalizing acceptance of the completed project deliverables. Verifying scope includes reviewing deliverables with the customer or sponsor to ensure that they are completed satisfactorily and obtaining formal acceptance of deliverables by the customer or sponsor.” PMBOK [5.4]